I need to do a custom outline for SystemVerilog. In this language, a collapsed line should be, for example, begin/end or class/endclass. Is it possible to not select words that have been commented out? I noticed for built in configurations like C++, the “{“ that are commented out do not get collapsed, which is what I am looking for.
blades018 wrote:
I need to do a custom outline for SystemVerilog. In this language, a collapsed line should be, for example, begin/end or class/endclass. Is it possible to not select words that have been commented out? I noticed for built in configurations like C++, the “{“ that are commented out do not get collapsed, which is what I am looking for.
Thanks
In EmEditor v9 alpha, the Outline plug-in was modified to ignore commented lines. You might want to try that new alpha version.
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